12-bit High-speed ADC (HSADC) Peripheral
The user manual UM10503 uses ADCHS to refer this peripheral. However the LPCOpen source code uses HSADC. This document will use HSADC excepts the register names used in the user manual.
Overview
The 12-bit high-speed ADC (HSADC) peripheral is only available on parts LPC4370 and LPC43S70.
Features
- 12-bit high-speed analog to digital converter.
- Input multiplexing among 6/3 pins.
- Descriptor based conversion sequence for single or multiple inputs.
- Integrated 14-bit timer
- Optional automatic high/low threshold detection.
- Power-down mode.
- Measurement range 0 to 1.2 V.
- 12-bit conversion rate of 80 MSamples/s.
- Optional conversion on transition on input pin or various internal signals.
- 16-word output FIFO with DMA support.
Channels and Pin Information
Table: Number of 12-bit high-speed ADC channels
| Order Number | Package | Number of 12-bit high-speed ADC pins (channels) |
|---|---|---|
| LPC4370FET256 | LBGA256 | 6 |
| LPC4370FET100 | TFBGA100 | 3 |
| LPC43S70FET256 | LBGA256 | 6 |
| LPC43S70FET100 | TFBGA100 | 3 |
Table: Pins for HSADC peripheral
| LBGA256 Package | TFBGA100 Package | Type | Description | |
|---|---|---|---|---|
| ADCHS_0 | E3 | A2 | I | 12-bit high speed ADC input channel 0 |
| ADCHS_1 | C3 | A1 | I | 12-bit high-speed ADC input channel 1 |
| ADCHS_2 | A4 | B3 | I | 12-bit high-speed ADC input channel 2 |
| ADCHS_3 | A5 | - | I | 12-bit high-speed ADC input channel 3 |
| ADCHS_4 | C6 | - | I | 12-bit high-speed ADC input channel 4 |
| ADCHS_5 | B3 | - | I | 12-bit high-speed ADC input channel 5 |
| ADCHS_NEG | B5 | A3 | I/O | 12-bit high-speed ADC reference voltage output or negative differentiate input |
To reduce interference, do not configure digital pins close to these pins.
Interrupts
This peripheral is connected to AHB bus, hence directly accessible by the M4 and M0 (aka M0APP) cores, except the M0 (aka M0SUB) subsystem core.
ADCHS interrupt is connected to
- Interrupt ID 45 to the M4's NVIC
- Interrupt ID 30 to the M0APP's NVIC
- Interrupt ID 30 to the M0SUB's NVIC
Clock Source
The base clock for HSADC is BASE_ADCHS_CLK, which is used to sample and convert data. This clock frequency (fADC) can be up to 80 MHz. The conversion takes one clock cycle. Data is available, after the conversion latency, in the output FIFO and channel output registers (LAST_SAMPLE0 to LAST_SAMPLE5).
Another
Its base clock is BASE_ADCHS_CLK. The clock source can be from
- IRC (default)
- 32 kHz oscillator
- ENET_RX_CLK
- ENET_TX_CLK
- GP_CLKIN
- Crystal oscillator
- PLL0 AUDIO
Basic Configuration
- Setup and enable clock to HSADC for register interface. The base clock is BASE_M4_CLK and the branch clock is CLK_M4_ADCHS.
- Setup and enable clock to HSADC sampling clock. The base clock is BASE_ADCHS_CLK_ _and the branch clock is CLK_ADCHS.
- Reset HSADC via ADCHS_RST which will clear everything.
- Setup FIFO for trip level and packing method